The present application relates generally to semiconductor devices, and more specifically to transistors such as field effect transistors and their methods of production.
The fabrication of semiconductor devices such as field effect transistors (FETs) typically involves multiple steps of layer deposition, patterning, and etching to define various structures on a substrate. Integration schemes using spacer and cap layers, for instance, may be used to precisely define respective conductive and insulating structures and accordingly minimize leakage between neighboring conductive structures to improve device performance.
In certain approaches, a contact etch stop layer (CESL) may be incorporated into the fabrication scheme to enable the selective removal of one or more layers. The unavailability of sufficiently etch-selective processes, however, and the attendant potential for damage to the contact etch stop layer may result in damage to protected layers, which may adversely affect manufacturing throughput and yield.